The evolvement of backplanes from bus-based architectures to fabric/mesh-based architectures has fueled rapid deployment of multi-gigabit serializer and de-serializer (SerDes) devices. The serializer does not transmit a dedicated clock signal. Instead the deserializer needs to have the capability to lock to the received data signal, extract the clock/timing information, retime/resample the received signal with the recovered clock, and make correct detections of the intended transmitted signal. As a result, the two key circuit blocks in the receiver are the clock and data recovery (CDR) and the equalizers (EQ). The former functions to extract the timing information and always ensures the data latches stay in the center of the data eye. The latter is to reshape the signal such that logic one is correctly distinguished from logic zero, and vice versa.
In addition, because of the leading edge speed of the SerDes devices, the serial data rates under test are generally faster than what the tester can support. So in many cases, looping back the Tx to Rx for a self test is used. However, a jitter free loopback test rarely represents the real application environment.
The industry recognized method of exercising the CDR circuit is through the compliance jitter tolerance (CJT) test. Jitter is defined as deviation of an actual signal edge from the ideal position, which has many contributing components (e.g. DCD, ISI, PJ, RJ, etc). The periodic jitter (PJ), also referred to as the sinusoidal jitter (SJ), is commonly used in jitter tolerance tests by modulating the signal before it reaches receiver inputs. Two parameters that define the periodic jitter are the jitter amplitude and the jitter frequency. The CDR circuit reacts differently to different periodic jitter frequencies. When the periodic jitter frequency is low and within the bandwidth of the CDR, the CDR could track the jitter and move along with the jittery signal edges. In that case, the recovered clock stays in the center of the data eye. However when the periodic jitter frequency goes higher than the CDR tracking band, the jitter cuts into the timing recovery margin for the CDR.
Precision periodic jitter generation has been an important component of electrical compliance test methodology on many serial data communication standards. Despite the importance of jitter testing, test methods and equipment targeted for volume production ATE applications are not widely available. This is partially attributed to the fact that the leading edge SerDes development has outpaced the tracking capability for many testing platforms including ATE.
Conventional ATE testing typically includes internal and external loopback tests. Although the PCB traces used in loopback create some ISI type of jitter, such jitter typically is not sufficient to provide a rigorous CDR stress test. It is typically difficult to control or even quantify the amount of ISI generated through these PCB traces. And because of layout constraints, it may not be possible to tune the traces length for a large number of SerDes ports on the same PCB. Therefore, loopback functional test alone is inadequate for CDR test coverage. As a result, the devices with marginal performance can escape from production test and cause system failures for the customers. Such problems are very difficult to debug once in a system and the replacement cost is extremely high.